In an asynchronous serial data link, there is no common clock connection between the device sending the data and the device receiving that data. The receiving device must extract (or recover) a clock from the transitions in the received data stream. Typically a phase-locked loop (PLL) is used to phase-lock to the received data and control the frequency of a new, local clock (the “recovered clock”). The recovered clock is then used to sample and re-time (“recover”) the received data.
FIG. 1A is a block diagram depicting a known clock and data recovery (CDR) circuit 100 according to the Background Art, corresponding to published U.S. Patent Application, Publication No. 2002/0021470. CDR circuit 100 includes: a half-rate phase detector 102; a charge pump 104; a low pass filter (LPF) 106; and a half-rate voltage-controlled oscillator (VCO) 108. Phase-detector 102 produces a signal that is proportional to the phase difference between the received data (Din) and a locally re-created clock (CK). The clock has a rate that is half of the rate of received data Din, hence phase detector 102 is described as a half-rate phase detector. Where Din has a rate of 10 Gb/sec, the rate of re-created clock CK is 5 GHz.
Charge pump 104 discharges or charges according to the output of phase-detector 102. VCO 108 receives a filtered (via LPF 106) output of charge pump 104, which represents a fine control input, and a relatively coarse control input, and re-creates the clock (CK).
Phase detector 102 also outputs two recovered data signals (DA and DB), each of which has a rate of 5 Gb/sec. Together, DA and DB represent a recovered and re-timed version of received data Din.
FIG. 1B is a more detailed block diagram of phase detector 102 according to the Background Art, which includes: a pair of data latches 122 and 124, a corresponding exclusive-OR (XOR) gate 126; another pair of data latches 128 and 130, and their corresponding XOR gate 132. It is noted that non-inverted signals in FIG. 1B have an inverted counterpart; for simplicity of illustration, however, the inverted counterparts have not been labeled, e.g., FIG. 1B does not show the labels Din, X1, etc.
Outputs X1 and X2 of latches 122 and 124 are combined by XOR gate 126 to produce the phase difference signal (labeled “ERROR” in FIG. 1B). Similarly, XOR 132 combines outputs Y1 and Y2 of latches 128 and 130, respectively. It is noted that, in contrast to signal ERROR, the output of XOR 132 does not vary in pulse width, hence it is given the label “REFERENCE.”